In the development of a system ASIC, the analog content often causes the most concern when attempting to achieve working
silicon on schedule. This situation is particularly true in the latest small-geometry processes, in which silicon turns are
costly and time-consuming. In addition, physical phenomena such as leakage currents and parasitic resistances and
capacitances are more significant.

Probably because of the supposed decline of analog circuits—and because it takes years to become proficient in this
difficult and diverse discipline—the availability of analog-IC design resources generally runs short of market demand.
The global market further exacerbates this shortage, because competition dictates reductions in time-to-market, and analog
circuit designs are typically on the critical path. As a consequence, companies construct design teams from around the globe,
picking specializations from different geographical sites wherever resources are available.

Cadence Design has been using multiple sites to custom-design predominantly analog ICs for many years. For example, I
recently worked on a team that completed a chip for UWB (ultrawideband) communication. The organization assigned a technical
lead and a program manager (the guy who takes care of all the project administration) with the design team split over two sites.
Here in Scotland, we developed a crystal oscillator and a high-frequency, low-jitter PLL. Simultaneously, our counterparts
in Maryland developed a fast, folding ADC and managed the top-level IC construction for a customer elsewhere in the United
States.

The two groups simultaneously designed circuit blocks and prepared the top level in parallel later in the design cycle.
Working in parallel made the design cycle somewhat more stressful but was essential to meet the market window. It was
helpful that the normal working hours of the different design offices overlapped; days did not need to be routinely
stretched to allow regular communication between sites. Videoconferencing, with the ability to share a whiteboard, served
as an excellent medium for discussing the circuits and for reviewing the design with the customer.

A design group can take a number of practical steps to facilitate multisite design. Fast networking across the world allows
distant teams to frequently update data between different locations. Our normal practice was to copy each site’s working
library to the other site during the night so that the complete, up-to-date database was available in both locations. This
step allowed cross-site review of designs, ensured that interfaces between blocks were compatible, and provided the
information for floorplanning the top level.

The analog designer gets a feel for his design as it progresses. He begins to understand how different parameters affect
the different specifications, and he carries a lot of related information in his mind. It is, at best, extremely inefficient
to try to time-multiplex the development of circuits, so design teams rarely adopt this approach. Instead, it is better to
parallel circuit development as much as possible.

Reusing analog circuits is becoming more important, both to extract value from existing analog IP (intellectual property)
and to provide a good initial starting point for new circuits. To improve the reuse process, it is useful to define standards
for analog IP. We work to our “Analog Design Manual,” which covers the directory structure for the development, including
the configuration and version of CAD tools and the versions of process data and cell libraries. The manual also lists styles
for drawing schematics so that designers can readily recognize aspects of the circuits, as well as signal-naming conventions
so that signal names automatically provide as much data as possible about their function. Standards take some overhead to
prepare and maintain, but in our experience, they have been very beneficial.

Gone are the days when an analog guru could use an artistic approach to develop circuit boards by judiciously inserting
capacitors here and there. Nowadays, when products rely on integration and demand high levels of performance, it is
important to maximize the probability of the best working silicon the first time. The approach must be much more precise
and scientific, but the satisfaction of seeing one’s creation operating on the bench or in products is still rewarding.